Summer break = Senior project

Last night I began my senior capstone project: a style sheet for ens0.info. For those not in the know, a style sheet is an editing tool used to create consistency in style, punctuation, abbreviations, units of measurement, and formatting.

I already have a rough plan in my head which would be better if I placed it in digital form, and this seems a good place to do so.

  1. Make an alphabet grid for unique words
  2. Add sections for capitalization, dates, numbers, etc.
  3. Determine which style Style Guide I’m using
  4. Determine which dictionary I’m using
  5. Define text layout
  6. Define font styles (this should be in the CSS already)
  7. Define visual layout principles

Once all those items are sorted out, I can begin reviewing the blog and filling in the style sheet. To complete the project, I’ll write up a short paper in which I explain my editing choices for organization, format (both text and overall), and the chosen terms in my grid.

Piece of cake, right?

The Visual Rhetoric of Frozen Pizza

Introduction

In a business as competitive as the packaged food industry, a fair amount of money must be put into attracting, or persuading customers to purchase your brand. While there are several means of doing this, there is none so persistent as having well designed labels. So while there is certainly a genre style to frozen pizza boxes, I aim to compare and analyze how various companies differently use color, images, and typography to attract customers. Continue reading

One down, two to go

By this time next week I will have finished my first semester as a technical writing major. I have but two more semesters in this long college run, and I’ll be happy to be done. I have to admit I made a mistake by not taking Dr. Heinsohn’s advice years ago, when she boggled at me when I told her I was a Comp Sci major, and she said I belonged in the liberal arts. I finally feel like I’m at home with this major. After years of trying to make myself love programming and heavy mathematics I have landed where I’ve always belonged.

Gopher is as gopher does

Super short post today: As of yesterday, I am a student at the University of Minnesota.

While I’m super excited at the possibilities presented here, I must admit it’s a bit overwhelming. I spent so long at my previous school, and was probably too comfortable there.

I hope to have enough time between courses to post about them, but if previous experience holds true, I’ll be too damned busy…

Digital Logic Design Project

The end of the semester is closing in, and the final projects have been assigned.

Here’s the one I drew:

Design a sequential circuit which adds six to a binary number in the range 0000 through 1001. The input and output should be serial with the least significant bit first. Find a state table with a minimum number of states. Design the circuit using NAND gates, NOR gates, and three D flip-flops. Any solution which is minimal for your state assignment and uses 10 or fewer gates and inverters is acceptable. (Assign 000 to the reset state.)

Test Procedure: First, check out your state table by starting in each state and making sure that the present output and next state are correct for each input. Then, starting in the reset state, determine the output sequence for each of the ten possible input sequences and make a table.

At first glance, it doesn’t sounds too complicated. Though, as with the first design project, I’m sure there are a ton of ways to get it working and minimize gate counts.

First order of business: Make a Truth Table!
I have omitted the “Don’t Cares” from this table, since my input range is restricted to inputs 0-9.

truth.table.16.4

Next, we need a State Diagram. We’ve spent very little time on these, so admittedly, I expect this part to be a bit more messy.

Lab Work – Flip flops.

“I said, a flip flop the flippie the flippie
To the flip flip flop, a you don’t stop
The rock it to the bang, bang boogie
Say up jumped the boogie
To the rhythm of the boogie, the beat”

My apologies to Sugarhill Gang…

Today’s lab project was considerably less complex than the one that preceded it. We’ve been studying flip-flops (though this is technically a latch), and the lab work today was to design a circuit using the same Quad NAND gate IC we’d been working with to create a SR-Bar latch.

In a nutshell: A flip-flop is able to store whatever state it’s been set to, high or low. It’s a circuit with a memory. Unlike the last section of lab, this one only took about an hour to get through from assignment to completion and being checked off by the instructor. I was pretty happy about that.

I even took a victory photo:

IMAG0287

Design Lab Work

Today’s Digital Systems Design lab somehow managed to totally confuse the hell out of me… Since I couldn’t seem to get anything done while I was there, I figured I would poke at it when I got home.

The basic gist of the assignment is this:

wire a simple logic circuit and look at its output to gain experience with
correct breadboarding techniques. Then we will look at how CMOS (complementary
metal-oxide-semiconductor) logic circuits differentiate between a logical 0 and logical 1 state. As you know, these circuits use voltage to determine logical states, so there is some threshold which the voltage must be clearly greater than or less than in order to correspond clearly to one of the states. The difference between the output voltage and the input threshold is known as the noise margin.

This assignment uses a Texas Instruments 74HC00 Quad NAND IC, hooked up to a function generator on the inputs, and output to a scope. The lab manual gave us these diagrams and a few pointers to get us going.

NAND_block

NAND.circuit

I also grabbed the datasheet from TI’s website, which gave me the pinouts.

IMG_0454

Each of the gates is labeled 1-4, with A & B inputs, and Y output. I’m still a bit confused as to how exactly the function generator, power supply, and scope plug into this, but I think I’ve managed to get a very pretty breadboard working here at home.

IMG_0453

All of the red wires are 5V positive, the black goes to ground, the green wire is the input to the function generator, and the yellow will connect to my scope. (I’ve since looped it like the green one.)

Oh yes, I must give credit for my fairly neat breadboards to Michael Ciuffo at ch00ftech for his awesome video advice about breadboarding. Basically, he’s got some of the slickest breadboard skills I’ve ever seen, and which you can watch here:

Sense of Accomplishment

This semester has been kind of hard on me. In addition to a crazy course load, I’ve had a lot of personal distractions going on, and settling into the role of a full time student has been a lot more difficult than expected.

So on the few occasions where I’ve really shined, I’m feeling rather proud of those moments. And tonight was a big one. My Digital Systems Design course has been a mixed bag. I did mediocre on the Boolean algebra, and now we’re designing circuits. Somehow, I seem to be pretty good at that especially now that we’re allowed some tools to help us out.

We’ve each been assigned a different final project for the course. The one I ended up with was this:

Design a circuit which multiplies two 2-bit binary numbers and displays the answer in decimal on a seven-segment indicator. In Figure 8-14, A and B are two bits of a binary number N1, and C and D are two bits of a binary number N2. The product (N1  N2) is to be displayed in decimal by lighting appropriate segments of the seven-segment indicator. For example, if A  1, B  0, C  l, and D  0, the number “4” is displayed by lighting segments 2, 3, 6, and 7.
Design your circuit using only two-, three-, and four-input NAND gates and inverters. Try to minimize the number of gates required.The variables A, B, C, and D will be available from toggle switches. Any solution that uses 18 or fewer gates and inverters (not counting the four inverters for the inputs) is acceptable.

Just 12 short hours ago, I was in class banging my head against the desk trying to figure out how to reduce the number of gates. (The count then was 20.) After much playing with Karnaugh Maps, some new solutions dawned upon me, re-groupings happened, and I managed to the my gate count down to 15!

I’m pretty sure that I’m in “A” territory for this project. Hopefully that will bring up my dreadful midterm grade in this course. (Curse you, Consensus Theorem!)

Here’s a peek at the final wiring diagram:
final.pics

Completely derailed

So, I’ve done just about nothing on the boat since school started. It seems between my homework load, and hours on the clock on campus there just isn’t enough time to finish off this toy. The nice thing is, since I’ll be taking some (but not many) courses over the summer term, I should be able to complete Serenity by early spring.

In semi-related news, I’ve been taking some tough classes. That said, having taken Physics might help out quite a bit with boat building once the spring thaw arrives.