This semester has been kind of hard on me. In addition to a crazy course load, I’ve had a lot of personal distractions going on, and settling into the role of a full time student has been a lot more difficult than expected.
So on the few occasions where I’ve really shined, I’m feeling rather proud of those moments. And tonight was a big one. My Digital Systems Design course has been a mixed bag. I did mediocre on the Boolean algebra, and now we’re designing circuits. Somehow, I seem to be pretty good at that especially now that we’re allowed some tools to help us out.
We’ve each been assigned a different final project for the course. The one I ended up with was this:
Design a circuit which multiplies two 2-bit binary numbers and displays the answer in decimal on a seven-segment indicator. In Figure 8-14, A and B are two bits of a binary number N1, and C and D are two bits of a binary number N2. The product (N1 N2) is to be displayed in decimal by lighting appropriate segments of the seven-segment indicator. For example, if A 1, B 0, C l, and D 0, the number “4” is displayed by lighting segments 2, 3, 6, and 7.
Design your circuit using only two-, three-, and four-input NAND gates and inverters. Try to minimize the number of gates required.The variables A, B, C, and D will be available from toggle switches. Any solution that uses 18 or fewer gates and inverters (not counting the four inverters for the inputs) is acceptable.
Just 12 short hours ago, I was in class banging my head against the desk trying to figure out how to reduce the number of gates. (The count then was 20.) After much playing with Karnaugh Maps, some new solutions dawned upon me, re-groupings happened, and I managed to the my gate count down to 15!
I’m pretty sure that I’m in “A” territory for this project. Hopefully that will bring up my dreadful midterm grade in this course. (Curse you, Consensus Theorem!)